ASIC Digital Design Engr, II Jobs in Bangalore - Synopsys Inc

ASIC Digital Design Engr II

Synopsys Inc

0 to 3 Years

Not disclosed

Expired

Posted: 08 Mar 21

Job Description

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.

Digital Design Verification Engineer
We’re looking for a highly motivated and innovative candidate to join our team.
Does this sound like a good role for you?

The Digital Design Verification Engineer works on PHY IP verification related to complex protocols. The position offers excellent learning and growth opportunities. This is a technical individual contributor role offering a challenging career path.

Key Qualifications

The role involves developing and working on verification of high speed PHYs and Serdes. Additionally you will be involved in:

BE/BTech +4 years of relevant experience / MTech +3 years of relevant experience in Electrical Engineering or other relevant field of study.
Verification plan development and its review
Verification environment development
Verification using internal or 3rd party VIP for the protocol of interest
Debug of simulations, including those of real signals modeled using SV for analog
RTL, GLS & Co-simulations & coverage closure
Participate in technical reviews and contribute actively
Follow and improve development process ensuring high quality output.

Preferred Experience

Knowledge of protocols like 25G/50G/100G Ethernet, PON, other networking protocols
Hands on experience in creating Verification Environment from Functional Specifications
Test planning, Coverage and Assertion planning
Hands on experience with System Verilog, mythologies like UVM, simulation and debug tools.
Experience with Version Control tools like Perforce/SVN.
Knowledge of Perl/Shell scripts

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.